1. Field of the Invention
This invention relates to a Field Programmable Gate Array (FPGA) incorporating peripheral routing with symmetrical edge termination at the boundaries. The invention also relates to a method for incorporating symmetrical edge termination at FPGA chip boundaries.
2. Description of the Related Art
FPGAs are programmable devices containing an array of programmable logic blocks connectable by programmable routing resources. IO pads at the chip periphery can interact with the core logic. The FPGA can be programmed to implement a wide range of circuits providing a large variety of designs. The efficiency of the implementation in terms of area and speed depends not only on the FPGA architecture, but also largely on effectiveness of the physical layout and interconnections. Automated software tools, known as automated Place & Route, define the connectivity provided by programmable interconnections. The automated Place & Route is a complex activity. An FPGA architecture that facilitates this activity can have a very considerably influence the quality of the output produced. A good architecture exploitable by the software is ideal. Symmetric architectures aid in the development of efficient software algorithms.
The problem of maintaining of symmetry is acute in the regions neighboring the chip periphery. The worst affected is the routing architecture. The Xilinx Virtex device attempts to correct this problem by reflecting back the lines hitting the edge [12] as shown in FIG. 1. This approach successfully maintains constant channel width in the FPGA. But at the same time two other changes occur:
1. A new switching module [11] is required to be defined at the periphery.
2. The segments no longer adhere to the properties demonstrated in the core.
A peripheral routing channel [13] is also introduced that is different from the core channel. These changes present new architectural components to be modeled by the software. These requirements introduce considerable complexities in the software algorithm resulting in inefficiencies and delays.
The XC 4000 architecture is relatively simple with a connection box interfacing the terminating core routing channel to the peripheral segments. Moreover, the XC 4000 routing employs single length line segments.